Design And Modelling An Attack on Multiplexer Based Physical Unclonable Function

This paper deals with study of the physical unclonable functions and specifically the design of arbiter based PUF (APUF) and extends the work on different types of attacks on the PUF designs to break the security of the device, which includes advanced computational algorithms. Machine learning (ML) based attacks are successful in attacking existing designs. So in this, the resistance of the modified, proposed design of APUF is examined by modelling the attack based on the logistic regression a MLbased algorithm. The design is validated on Basys-3 Artix -7 FPGA board with a part number (xc7a35tcpg236-1).

READ FULL TEXT
research
06/24/2020

Subpopulation Data Poisoning Attacks

Machine learning (ML) systems are deployed in critical settings, but the...
research
05/28/2021

The Unpatchable Silicon: A Full Break of the Bitstream Encryption of Xilinx 7-Series FPGAs

The security of FPGAs is a crucial topic, as any vulnerability within th...
research
05/10/2023

Similarity-Based Logic Locking Against Machine Learning Attacks

Logic locking is a promising technique for protecting integrated circuit...
research
01/06/2023

Linear and non-linear machine learning attacks on physical unclonable functions

In this thesis, several linear and non-linear machine learning attacks o...
research
03/07/2023

Word-Level Structure Identification In FPGA Designs Using Cell Proximity Information

Reverse engineering of FPGA based designs from the flattened LUT level n...
research
11/06/2021

On pseudo-absence generation and machine learning for locust breeding ground prediction in Africa

Desert locust outbreaks threaten the food security of a large part of Af...
research
06/02/2022

A New Security Boundary of Component Differentially Challenged XOR PUFs Against Machine Learning Modeling Attacks

Physical Unclonable Functions (PUFs) are promising security primitives f...

Please sign up or login with your details

Forgot password? Click here to reset