Delay Monitor Circuit for Sensitive Nodes in SRAM-Based FPGA

07/30/2018

∙

This paper presents a novel monitor circuit architecture and experiments performed for detection of extra combinational delays in a high frequency SRAM-Based FPGA on delay sensitive nodes due to transient ionizing radiation.

READ FULL TEXT

Delay Monitor Circuit for Sensitive Nodes in SRAM-Based FPGA

EffiTest: Efficient Delay Test and Statistical Prediction for Configuring Post-silicon Tunable Buffers

Radix-2 Self-Recursive Sparse Factorizations of Delay Vandermonde Matrices for Wideband Multi-Beam Antenna Arrays

Implementation of Digital Circuits on Three-Dimensional FPGAs Using Simulated Annealing

Reliability-Aware Overlay Architectures for FPGAs: Features and Design Challenges

Monitoring hyperproperties with circuits

Synaptic Delays for Temporal Feature Detection in Dynamic Neuromorphic Processors

Delay Monitor Circuit for Sensitive Nodes in SRAM-Based FPGA

Related Research

EffiTest: Efficient Delay Test and Statistical Prediction for Configuring Post-silicon Tunable Buffers

Radix-2 Self-Recursive Sparse Factorizations of Delay Vandermonde Matrices for Wideband Multi-Beam Antenna Arrays

Implementation of Digital Circuits on Three-Dimensional FPGAs Using Simulated Annealing

Reliability-Aware Overlay Architectures for FPGAs: Features and Design Challenges

Monitoring hyperproperties with circuits

Synaptic Delays for Temporal Feature Detection in Dynamic Neuromorphic Processors