DeepAI AI Chat

Content Addressable Parallel Processors on a FPGA

06/21/2021

∙

by Ayush Salik, et al.

∙

University of Massachusetts Amherst

∙

∙

In this short article, we report on the implementation of a Content Addressable Parallel Processor using a FPGA. While Content addressable memories have been implemented in FPGAs, to our knowledge this is the first implementation in FPGA of Caxton C. Foster's vision of parallel processing, particularly the notions of parallel write as well as the combining of output values, which are usually missing in more typical CAM implementations, such as the ones designed for network routing. The resulting CAPP is made accessible to a host computer over a USB/UART interface, using a straightforward serial protocol that is demonstrated using a Python-based driver.

Ayush Salik
1 publication
Manor Askenazi
1 publication
Edward Rietman
1 publication

page 1

page 2

page 3

page 4

∙ 09/17/2018

Design and Implementation of High-throughput PCIe with DMA Architecture between FPGA and PowerPC

We designed and implemented a direct memory access (DMA) architecture of...

0 Kun Cheng, et al. ∙

∙ 06/23/2018

A readout method based on 10 Gigabit Ethernet for Sipixel detector

With the rapid development of network protocol, TCP/IP has been widely a...

0 Hangxu Li, et al. ∙

∙ 09/30/2016

Caffeinated FPGAs: FPGA Framework For Convolutional Neural Networks

Convolutional Neural Networks (CNNs) have gained significant traction in...

0 Roberto DiCecco, et al. ∙

∙ 02/15/2023

An Implementation of a Dual-Processor System on FPGA

In recent years, Field-Programmable Gate Arrays (FPGA) have evolved rapi...

0 Mohammed Eqbal Eshaq, et al. ∙

∙ 02/28/2022

Multi-FPGA Designs and Scaling of HPC Challenge Benchmarks via MPI and Circuit-Switched Inter-FPGA Networks

While FPGA accelerator boards and their respective high-level design too...

0 Marius Meyer, et al. ∙

∙ 05/31/2018

A Highly Parallel FPGA Implementation of Sparse Neural Network Training

We demonstrate an FPGA implementation of a parallel and reconfigurable a...

0 Sourya Dey, et al. ∙

∙ 02/10/2020

A portable and Linux capable RISC-V computer system in Verilog HDL

RISC-V is an open and royalty free instruction set architecture which ha...

0 Junya Miura, et al. ∙