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hxtorch: PyTorch for ANNs on BrainScaleS-2
We present software facilitating the usage of the BrainScaleS-2 analog n...
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FPSA: A Full System Stack Solution for Reconfigurable ReRAM-based NN Accelerator Architecture
Neural Network (NN) accelerators with emerging ReRAM (resistive random a...
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Entropy-Based Modeling for Estimating Soft Errors Impact on Binarized Neural Network Inference
Over past years, the easy accessibility to the large scale datasets has ...
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Optimally Scheduling CNN Convolutions for Efficient Memory Access
Embedded inference engines for convolutional networks must be parsimonio...
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Giving Text Analytics a Boost
The amount of textual data has reached a new scale and continues to grow...
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SESAME: Software defined Enclaves to Secure Inference Accelerators with Multi-tenant Execution
Hardware-enclaves that target complex CPU designs compromise both securi...
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XNOR Neural Engine: a Hardware Accelerator IP for 21.6 fJ/op Binary Neural Network Inference
Binary Neural Networks (BNNs) are promising to deliver accuracy comparab...
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Compiling Neural Networks for a Computational Memory Accelerator
Computational memory (CM) is a promising approach for accelerating inference on neural networks (NN) by using enhanced memories that, in addition to storing data, allow computations on them. One of the main challenges of this approach is defining a hardware/software interface that allows a compiler to map NN models for efficient execution on the underlying CM accelerator. This is a non-trivial task because efficiency dictates that the CM accelerator is explicitly programmed as a dataflow engine where the execution of the different NN layers form a pipeline. In this paper, we present our work towards a software stack for executing ML models on such a multi-core CM accelerator. We describe an architecture for the hardware and software, and focus on the problem of implementing the appropriate control logic so that data dependencies are respected. We propose a solution to the latter that is based on polyhedral compilation.
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