1. Introductory dialog
Q^{1}^{1}1Quisani, a former student of the second author: Tell me please what quantum circuits are exactly.
A^{2}^{2}2The authors speaking one at a time: Can’t you consult a textbook on quantum computations?
Q: What textbook? Maybe I am being silly or unlucky, but I looked up many textbooks on quantum computations, including the standard text [7]. Nobody seems to define quantum circuits carefully. Furthermore, nobody seems to define reversible Boolean circuits carefully, at least in the books that I got hold of [1, 4, 6, 8].
A: Four of our Michigan colleagues wrote a good paper on the synthesis of reversible Boolean circuits [9]. They say that a gate is reversible if “the (Boolean) function it computes is bijective” and that a reversible Boolean circuit is “an acyclic combinational logic circuit in which all gates are reversible, and are interconnected without fanout.”
Q: Hmm, I have never heard of combinational logic circuits.
A: The terminology seems to be used primarily in electrical engineering. But tell us more about what bothers you.
Q:
Presumably, quantum circuits constitute a straightforward generalization of reversible Boolean circuits. But the generalization cannot be too straightforward. A Boolean circuit, furnished with input, allows you to assign Boolean values to each edge of the circuit. As a result it is crystal clear that different ways to evaluate a given circuit on a given input produce the same output. In the case of a quantum circuit with input, you can assign values to edges but, as far as I can see, this isn’t nearly as useful as in the Boolean case. Everybody seems to consider it obvious that different ways to evaluate a given quantum circuit on a given input produce the same output. This is probably true but it needs a proof. Besides, what is the Boolean analog for measurements?
A: We hear you. It is all about circuit pedantry. But let’s forget about measurements for the time being, so that our quantum circuits are unitary in the sense that the transformation performed by any gate is unitary.
Q: OK, I’ll bug you about measurements later. Give me a general plan of circuit pedantry as you see it.
A: Boolean circuits and unitary quantum circuits have much in common, especially if you abstract from what transformations are assigned to circuit gates. The graphtheoretical foundations are very similar. In this connection, in §2, we introduce syntactic circuits. The definition of syntactic circuits simplifies in the case of circuits underlying reversible Boolean circuits and unitary quantum circuits; we call them balanced circuits. Syntactic circuits support various semantics.
In §3 we look at the semantics of general Boolean circuits and the simplified semantics of Boolean circuits which are balanced in the sense that the underlying syntactic circuits are balanced. Reversible Boolean circuits are special balanced Boolean circuits.
In §4 we look at the semantics of unitary quantum circuits. We’ll verify that different evaluations of such a circuit on a given input indeed produce the same result.
2. Syntactic circuits
In this section we define a syntactical notion of circuit. It is a graphical structure involving gates which are treated as black boxes. The Boolean semantics and quantum semantics of circuits will be defined in subsequent sections.
2.1. Definition
Recall that a directed multigraph is a 4tuple where is a set of vertices, also called nodes, is a set of edges, and Source, Target are functions of type which assign to each edge its source and target nodes respectively. The multigraph is finite if and are finite.
A (nonempty directed) walk in a multigraph is a nonempty sequence of edges which connects nodes so that and for every edge . We say that this walk is a walk from to , and that all the nodes are involved in the walk. The walk is a path if all the nodes are distinct; it is a cycle if the nodes are distinct except that . The multigraph is acyclic if it has no cycles. In an acyclic multigraph, every walk is a path.
Definition 1 (Syntactic circuits).
A syntactic circuit or simply a circuit is a finite acyclic directed multigraph with no isolated nodes and with some additional structure as follows.

The nodes are classified as
input nodes, output nodes, and gates. 
The input nodes are linearly ordered, and each of them has at least one outgoing edge and no incoming edge. The edges from input nodes are input edges.

The output nodes are linearly ordered, and each of them has exactly one incoming edge and no outgoing edge. The edges to output nodes are output edges.

Every gate has at least one incoming edge and at least one outgoing edge.
We say that a node of a circuit is earlier than another node if there is a path from to . This relation is a (strict) partial order because the circuit is acyclic.
The depth of a circuit is the maximum number of gates involved in any path.

Q: Why do you insist on ordering the input and output nodes?
A: These orderings are used in computations. Because of these orderings, the inputs and outputs of Boolean circuits are tuples of Boolean values rather than indexed sets of Boolean values. In a spirit of describing rather than prescribing how to work with circuits, we employ the orderings.
2.2. Balanced circuits
Definition 2.
A gate of a circuit is balanced if the number of incoming edges equals the number of outgoing edge. That number is the arity of the gate.
It is common to represent a balanced ary gate by a diagram
@C=2em @R=0em
& 5G &
& G &
& G &
& G &
& G &
& G &
with incoming edges on the left and outgoing edges on the right, so that time flows left to right.
Definition 3.
A circuit is balanced if

all its gates are balanced, and

the number of input nodes coincides with the number of output nodes.
The number of input nodes is the width of a balanced circuit.
The diagram representation of balanced gates naturally extends to balanced circuits. Here is a simple example [5] of a widththree circuit
@C=1em @R=.7em
& 1G_1 & G_22 &
& G_1 & &
& & G_2 &
with two binary gates. Let us use this example to illustrate convenient terminology that we will be using.
There are three horizontal strata of edges of the diagram. We follow common terminology calling these strata timelines. (This terminology is not intended to mean that some physical entity is propagating along each line.) We number the timelines from top to bottom in diagrams. Both gates and encounter timeline 1. encounters timeline 2 but doesn’t. encounters timeline 3 but doesn’t. We say that a gate is active on the timelines it encounters. Thus gate is active on timelines 1 and 3.
Proposition 4.
In any balanced circuit, the input nodes have exactly one outgoing edge each.
Proof.
Consider a timeline diagram of a given circuit, and let be the width of the circuit. The key observation is that the number of timelines remains constant throughout the diagram because all the gates are balanced. At end of the diagram, the timelines are represented by output edges, so the number of timelines is . If at least one input node has two or more outgoing edges then the number of timelines would be which is impossible. ∎
Remark 5.
A bit more generally, in a circuit where all gates are balanced the number of input edges equals the number of output edges which equals the number of output nodes. Such a circuit is balanced if and only if no input node fans out.
2.3. Composition theory
In the rest of this section, by default, circuits are balanced.
Definition 6 (Composition).
Let be disjoint circuits of the same width . The composition is the circuit of width constructed from thus. At each one of the strata, merge the output edge of and the input edge of into one edge, removing the output node of and the input node of in the process.
If are not disjoint, replace them with isomorphic copies that are disjoint. The composite is defined only up to isomorphism. Composition of circuits is associative, so the composite is defined for any . For , we adopt the standard convention that the composite of a single circuit is that circuit.
A gate set (i.e. a set of gates) in a circuit is convex if every path from an gate to an gate involves only gates.
Definition 7 (Slice).
Let be a convex gate set of a circuit . The slice of generated by is a circuit of the width of constructed from as follows.

Remove all non gates as well as all edges such that neither nor belongs to .

On every timeline where some gate is active, do the following. If the input edge has been removed then attach the input node to the unique sourceless edge on the timeline. If the output edge has been removed then attach the output node to the unique targetless edge on the timeline.

On every timeline with no active gates, restore the removed input edge and, if the input edge isn’t also the output edge, attach the output node to it.

Q: Stage (3) looks artificial. Instead of restoring input edges, it seems more natural to create fresh edges.
A: It is a bit artificial but for a reason. Notice that the slice generated by is completely determined by , that is if is the slice generated by and so is then and are identical, not almost identical but completely identical.
Q: Is this important?
A: Not really, but it simplifies the exposition, and the price for simplification is small.
A sequence of gate sets of a circuit is coherent if it respects the relation “earlier” in the sense that whenever some node of is earlier than some node of . A sequence of gate sets of is a coherent partition of the gates if it is coherent and if the sets partition the gates of .
Definition 8.
A decomposition of a circuit is a representation of as a composite where

every is the slice of generated by a convex subset of the gates of ,

the sequence is a coherent partition of the gates of .
Theorem 9.
Let be a balanced circuit.

Any decomposition of gives rise to a coherent partition of the gates where each comprises the gates of .

Any coherent partition of the gates gives rise to a decomposition
where each factor is the slice generated by (and thus completely determined, not just up to isomorphism).
Proof.
The first claim follows directly from the definition of decomposition.
We prove the second claim by induction on . The case is trivial. Suppose that . Then is the composite where is the slice of generated by the convex gate set . By the induction hypothesis, , and therefore . The definition of slice implies that the factors are completely determined. ∎
A subset of the gates of a circuit is an antichain if every two gates are incomparable, so that neither is earlier than the other. In particular, antichains are convex. Notice that a slice is generated by a nonempty antichain if and only if its depth is 1.
Corollary 10.
Let be a balanced circuit.

Any decomposition of into depth1 factors gives rise to a coherent partition of the gates into antichains , where each is the gate set of .

Any coherent partition of the gates into antichains , …, gives rise to a decomposition of into depth1 factors
where each factor is the slice generated by (and completely determined).
The index in Corollary 10 alludes to time as will become clear as we discuss semantics in the next two sections.
Definition 11.
For any circuit , a coherent gate linearization is a linear ordering of all the gates which extends the relation “earlier”, so that if is earlier than then .
Corollary 12.
Let be a balanced circuit with gates.

Any decomposition of into onegate factors gives rise to a coherent gate linearization where each is the only gate of .

Any coherent gate linearization gives rise to a decomposition into onegate factors
where each factor is the slice generated (and completely determined) by .
3. Boolean circuits
The syntax of Boolean circuits has been defined in the previous section. In this section, we define the semantics.
The central role in Boolean semantics is played by the notion of bit. For computational purposes, a bit is a variable with two possible values and . Alternatively, a bit can be viewed as a physical system which can be in one of two possible states represented by and . The first point of view is common in computer science, the second is natural for physics. For brevity, we call them logical and physical. In this section, the logical point of view will be dominant. The physical point of view is useful as well. In the next section, it will support the generalization of Boolean semantics to quantum semantics.
3.1. Definition
A Boolean function is a function of type where are natural numbers. It transforms a state of an bit system to a state of an bit system. For example, the functions
are of type . Here are the standard graphical representations
@C=2em @R=1.5em
&1 &
&&
@C=2em @R=2em
& [1] &
& &
of cNot and Swap respectively. The function cNot is known as controllednot. The first argument (represented by the black dot) is the control and the second (represented by the circle) is the target.
Definition 13.
A Boolean circuit is a syntactic circuit together with an assignment of the following to each gate .

A Boolean function of type where are the numbers of incoming and outgoing edges of respectively.

A onetoone correspondence between the incoming edges of and the argument positions of . The edge associated with the th argument position is the th argument edge of .

A onetoone correspondence between the outgoing edges of and the value positions of . The edge associated with the th value position is the th value edge of .
3.2. Valuations
Let be a Boolean circuit with input nodes. An input to is an assignment of Boolean values to the input nodes in order. The binary string determines and can be identified with the input.
Definition 14.
A valuation of on a given input is a Booleanvalued function Val on the edges of such that

if emanates from the th input node then , and

if is the th value edge of a gate assigned Boolean function and are the 1st, 2nd, etc. argument edges of , then .
Theorem 15.
There is a unique valuation of any given Boolean circuit on any given input.
Proof.
Construct the desired valuation, in a unique way, by induction on the ordering “ is earlier than ”. ∎
The function of is the Boolean function
where are the Boolean values assigned to the output edges number respectively by the valuation of on input .
View a Boolean circuit as a computing device that, given an input binary string , computes the unique valuation on the input and then outputs . That computation may be executed by one computing agent or several computing agents which collaborate in performing the circuit computation. In either case, if gate is earlier than gate then must be fired, or executed, before is fired. Incomparable gates may be fired in either order or simultaneously.
We restrict attention to the case where circuit computations are performed by one computing agent executing one step after another.
There may be different such sequentialtime computations of a given circuit on a given input. One of them is the eager computation:
until all gates are fired do
fire all of the earliest unfired gates.
In a general computation, only some of the earliest gates are fired at step 1, only some of the earliest among the remaining gates are fired at step 2, and so on.
Theorem 16.
All computations of any given Boolean circuit on any given input produce the same valuation and the same output.
Proof.
Each computation of a given circuit on a given input produces a valuation. All these valuations coincide because there is only one valuation of on . It follows that all the outputs coincide. ∎
3.3. Balanced Boolean circuits
We turn attention to Boolean circuits whose underlying syntactic circuits are balanced. We simplify the description of such Boolean circuits by imposing a normalizing constraint on the correspondences of incoming and outgoing edges of a gate to the argument and value positions respectively of the Boolean function assigned to the gate.
Definition 17.
A balanced Boolean circuit is a balanced syntactic circuit together with an assignment of the following to each gate .

A Boolean function of type where is the arity of .

If is active on timelines then the incoming and outgoing edges of timeline are assigned to the th argument position and the th value position of , so that they are the th argument edge and th value edge of respectively.
The simplification reflects common practice. It is not without a price. One should pay attention to how the argument (resp. value) positions of the assigned Boolean function are ordered. For example, one should distinguish between these two versions of the cNot function:
@C=2em @R=1.5em
&1 &
&&
@C=2em @R=1.5em
&&
&1 &
Remark 18.
This simplification exploits the linear ordering of timelines on the timeline diagrams that we use to represent balanced syntactic circuits. The incoming (resp. outgoing) edges of a gate inherit that order. The general Boolean circuits can be similarly simplified if appropriate linear orderings of the incoming (resp. outgoing) edges of each gate are provided.
In the rest of this section, Boolean circuits are by default balanced.
Definition 19.
The composition, also called the product, of Boolean circuits with underlying syntactic circuits respectively is a Boolean circuit whose underlying syntactic circuit is the composition . On the gates inherited from the gate assignment of coincides with that of .
As in the case of syntactic circuits, the composite circuit is defined only up to isomorphism.
The composition of Boolean functions of the same arity is defined as usual:
Proposition 20.
If a Boolean circuit is the composite of Boolean circuits computing Boolean functions respectively then
Proof.
Definition 21.
A decomposition of a Boolean circuit is a representation of as a composite such that the composite of the underlying syntactic circuits is a decomposition of the underlying syntactic circuit of .
Notice that the factors are completely determined by the underlying gate sets.
Definition 22.
Let be a balanced Boolean circuit.

A Boolean circuit is a slice of if the underlying syntactic circuit of is a slice of and the gate assignment of coincides with that of on the gates.

A coherent gate linearization of is that of the underlying syntactic circuit of , that is a linear extension of relation “earlier” on the gates.
Theorem 23.
Let be a balanced Boolean circuit.

Any decomposition of gives rise to a coherent partition of the gates where each comprises the gates of .

Any coherent partition of the gates gives rise to a decomposition
where each factor is the slice of generated by (and completely determined).
Proof.
This is a straightforward consequence of Theorem 9 ∎
Corollary 24.
Let be a balanced Boolean circuit.

Any decomposition of into depth1 factors gives rise to a coherent partition of the gates into antichains , where each is the gate set of .

Any coherent partition of the gates into antichains , , …, gives rise to a decomposition into depth1 factors
where each factor is the slice generated by (and completely determined).
Corollary 25.
Let be a balanced Boolean circuit with gates.

Any decomposition of into onegate factors gives rise to a coherent gate linearization where each is the only gate of .

Any coherent gate linearization of the gates gives rise to a decomposition into onegate factors
where each factor is the slice generated by (and completely determined).
Define the depth of a Boolean circuit to be the depth of the underlying syntactic circuit , that is the maximum number of gates involved in any path.
Theorem 26.
Let be the depth of a balanced Boolean circuit , and consider computations of on a given input.

Any computation has at least steps.

The eager computation has exactly steps.

For some choices of , there are noneager step computations.
Proof.

Since a gate cannot be fired until all the earlier gates have been fired, the last gate involved in a longest path can not be fired before step .

Obvious.

Consider a coherent partition the gates where comprises the latest gates, and comprises the latest among the remaining gates, and so on. It gives rise to a step computation which may be different from the eager computation. (This computation procrastinates as much as possible subject to finishing in steps.) ∎
3.4. Reversible Boolean circuits
A function of type has a (twosided) inverse if and only if and is a permutation of . The inverse is unique; it is the inverse of in the permutation group of . For example the controllednot function is its own inverse.
Definition 27.
A Boolean function is reversible if it has a (twosided) inverse. A Boolean circuit is reversible if its function is reversible.
Lemma 28.
The composite of Boolean circuits is reversible if and only if each factor is reversible.
Proof.
Let be the functions of circuits , respectively. We prove that is reversible if and only every is reversible. The “if ” implication is obvious.
The “onlyif ” implication is proved by contrapositive. Suppose that some is irreversible, and let , so that for some . Let be the products of functions and functions , respectively. Our choice of implies that is reversible. Let and . We have but
so that is irreversible. ∎
Corollary 29.
A Boolean circuit is reversible if and only if all its gates are reversible.
Proof.
Consider a circuit with gates and recall that the gates are partially ordered by relation “earlier”. Choose a linear order of the gates which respects relation “earlier”. By Corollary 25, there is a decomposition where is the slice of generated by so that is reversible if and only if is reversible. Now apply Lemma 28. ∎
4. Quantum circuits
The syntax of quantum circuits is that of Boolean circuits and is defined in §2. In this section, we define the semantics. However, we impose an important constraint on the circuits under consideration.
Proviso 30.
We restrict attention to unitary quantum circuits, that is quantum circuits where all gate operators are unitary. Below, quantum circuits are by default unitary.

Q: In other words, a unitary circuit is a circuit without measurements.
A: It is essentially so. But unitary operators can be seen as degenerate singleoutcome measurements. See for example the general definition of quantum measurements in §2.2.3 of [7]. So, more pedantically, a unitary circuit is a circuit where the only measurements are degenerate ones.
4.1. Definition
In a sense, quantum circuits generalize balanced Boolean circuits. The role of a bit, as a physical system, is played by a qubit which is a quantum system with state space and a fixed orthonormal basis , known as the computational basis. The study of Boolean circuits above, in §3, readily generalizes to the case where twostate physical systems (bits) are replaced with state physical systems for any fixed positive integer
. Similarly, the study of quantum circuits below readily generalizes to the case where qubits are replaced with qudits, with state space
, for any fixed positive integer .Because of entanglement, the Booleantoquantum generalization is not straightforward. In particular, the idea of assigning values to the edges of a given circuit is too simplistic for the quantum case.
Dealing with multiqubit systems, we will always presume that the qubits are distinguishable. The combined system of qubits will be denoted . The state space of the combined system is where and .
Definition 31.
A (unitary) quantum circuit of width is a balanced syntactic circuit of width together with the following assignments.

Inputs are assigned distinct qubits in order. These qubits are the qubits of , and the combined system is the physical system of .

Each gate is assigned a unitary operator . If the arity of is and encounters timelines , then operates on (the state space of) the subsystem of .
The intention is that describes an evolution of its physical system .
The state space of has dimension . Its orthonormal computational basis
comprises vectors
where ranges over the set of binary strings of length . Every permutation of gives rise to a permutation of the basis vectors of which, by linearity, extends in a unique way to a unitary operator
The resulting unitary operator often shares the name of the original permutation. Thus we have unitary operators cNot and Swap on .
Of course, unitary operators do not have to merely permute the basis vectors. But, by linearity, any unitary operator is determined by its action on the basis vectors. Here are two important unitary operators on :
The operator is known as the Hadamard operator.
4.2. Combinatorics
We interrupt our circuit exposition in order to prove an auxiliary combinatorial result (which is probably known but we failed to find it in the literature).
Call a linear order on a poset (partially ordered set) coherent if whenever .
A linear order on a finite set can be transformed into any other linear order on by adjacent transpositions. In other words, there is a sequence , of linear orders such that is , and is , and every is obtained from by transposing one pair of adjacent elements of . The question arises whether, if and are coherent with a partial order , the intermediate orders in the transposition sequence can also be taken to be coherent with . The following theorem answers this question affirmatively.
Theorem 32.
Any coherent linear order on a finite poset can be transformed into any other coherent linear order on by adjacent transpositions with all intermediate orders being coherent.
Proof.
Fix a finite poset . We start with an observation that if two elements are ordered differently by two coherent linear orders then are incomparable by . Indeed, if were comparable then one of the two linear orders would not be coherent.
Define the distance between two coherent linear orders and to be the number of differentiating pairs such that but . We claim that if then there is a differentiating pair such that are adjacent in ordering . It suffices to prove that if is a differentiating pair and then either or is a differentiating pair, so that or . But this is obvious. If then which is false.
We prove the theorem by induction on the distance between two given coherent linear orders and . If , the two orders are identical and there is nothing to prove. Suppose .
By the claim above there exist such that are adjacent in but . By the observation above, are incomparable by . Let be the order obtained from by transposing the adjacent elements and . is coherent because is the only differentiating pair and because are incomparable by .
It remains to prove that can be transformed into by adjacent transpositions with all intermediate linear orders respecting . But this follows from the induction hypothesis. Indeed, because the differentiating pairs are the same as the differentiating pairs, except for . ∎
4.3. Quantum circuit computations
Consider a quantum circuit with physical system . Assume that initially is in state . Computationally, is an input of .
We say that a gate is active at qubit if encounters timeline . It will be convenient to view the unitary operator operating on the whole system and not only on the subsystem formed by the qubits where is active at; works as the identity operator at every qubit where is not active.
If gates of form an antichain then they are active at disjoint sets of qubits and therefore the operators commute and can be executed in an arbitrary order or simultaneously; their combined action is a unitary operator which will be denoted .
Any computation of on the given input works in sequential time, step after step. At each step an antichain of gates is executed. This determines a coherent partition of the gates into antichains where comprises the gates executed at step and is the number of steps. (This is why we chose the symbols and , as allusions to “time”.) Any coherent antichain partition of the gates uniquely determines a computation of on the given input where are executed in order; and so the computation can be identified with the coherent antichain partition.
Any computation of on the given input determines a sequence
of states of where every , and is the final state and the output of the computation.
Theorem 33.
For any quantum circuit , any two computations of on any fixed input produce the same output.
Proof.
In this proof, a computation means a computation of on input . Two computations will be called equivalent if they produce the same input. A computation will be called linear if a single gate is executed at every step.
First we notice that every computation is equivalent to a linear computation. For the sake of completeness, we provide a proof of this claim. Define the linearity deficit of a computation to be the number of gates executed at the same step of as at least one other gate. It suffices to show that every computation with positive is equivalent to a computation with . To this end, let be a computation with and the first antichain in with at least two gates. Further, let be any of the gates and . Split step into two smaller steps: first execute and then all the gates, and let be the resulting computation. Clearly . Since is an antichain, the unitary transformations and commute, and therefore the product . It follows that is equivalent to .
It remains to prove that any two linear computations are equivalent. Any linear computation constitutes a linear ordering that is coherent in the sense that it respects the relation “earlier” on the gates. By Theorem 4.2, any coherent linearization can be transformed to any other coherent linearization by adjacent transpositions with all intermediate orders being coherent. Accordingly it suffices to prove linear computations and are equivalent if is obtained from by one adjacent transposition. To prove that, let be obtained from by transposing gates and . These two gates are incomparable. Indeed, if were earlier than then would be incoherent, and if were earlier than then would be incoherent. It follows that the two gates are active on disjoint sets of qubits of . Therefore and commute, , and therefore the two linear computations are equivalent. ∎
4.4. Generalizations
Q: If I understood you correctly, the Boolean semantics of §3 easily generalizes from the standard 2valued variables (bits) to valued variables, for any fixed . And quantum semantics easily generalizes from qubits, with state space , to qudits, with state space , for any fixed . I think I understand the generalizations. They require no change of syntactic circuits. By the way, I found some papers that actually use qudits with [2, 3].
But why keep fixed? Let vary. In a classical (in contrast to quantum) circuit, one input node could be 2valued while another could be 3valued. A quantum gate might have a qubitcarrying incoming edge and a qutritcarrying one. The details seem easy to fix. Am I missing something?
A: Reversibility imposes an important constraint. Consider a gate with incoming edges of capacities and with outgoing edges of capacities . The constraint is
(1) 
Q: Explain.
A: In the classical case, let be the function assigned to . In order for to be reversible, the domain and codomain of should have exactly the same number of elements. In other words, the number of possible input tuples should be equal to the number of possible output tuples. Hence equation (1). When all the capacities were just 2, this meant simply that , as in our definition of balanced circuits, the underlying syntactic circuits of reversible Boolean circuits. But with general capacities, the equation (1) does not reduce to .
In the quantum case the situation is similar. Let be the transformation assigned to . The domain of is , and the codomain of is . In order for to be reversible, the dimension of the domain and the dimension of the codomain should be equal. Hence equation (1).
References
 [1] Anas N. AlRabadi, “Reversible logic synthesis,” Springer 2004
 [2] Alex Bocharov, Martin Roetteler and Krysta M. Svore, “Factoring with qutrits: Shor’s algorithm on ternary and metaplectic quantum architectures,” Physical Review A 96 012306 2017
 [3] Earl T. Campbell, Hussain Anwar and Dan E. Browne, “Magic state distillation in all prime dimensions using quantum ReedMuller codes,” Physical Review X 2, 041021 2012
 [4] Alexis De Vos, “Reversible computing: Fundamentals, quantum computing, and applications,” WileyVCH 2010

[5]
Bryan Eastin and Steve T. Flammia,
“Qcircuit tutorial,”
http://physics.unm.edu/CQuIC/Qcircuit/Qtutorial.pdf  [6] Kenichi Morita, “Theory of reversible computing,” Springer 2017
 [7] Michael A. Nielsen and Isaac L. Chuang, “Quantum computation and quantum information,” Cambridge University Press, 10th Anniversary Edition, 2010
 [8] Kalyan S. Perumala, “Introduction to reversible computing,” CRC Press 2014
 [9] Vivek V. Shende, Aditya K. Prasad, Igor L. Markov, and John P. Hayes, “Synthesis of reversible logic circuits,” IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems 22:6 710–722 2003
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