Block-matching in FPGA

06/24/2020

∙

Block-matching and 3D filtering (BM3D) is an image denoising algorithm that works in two similar steps. Both of these steps need to perform grouping by block-matching. We implement the block-matching in an FPGA, leveraging its ability to perform parallel computations. Our goal is to enable other researchers to use our solution in the future for real-time video denoising in video cameras that use FPGAs (such as the AXIOM Beta).

READ FULL TEXT

Block-matching in FPGA

Block-Matching Convolutional Neural Network for Image Denoising

New Computational Techniques for a Faster Variation of BM3D Image Denoising

Low Latency Video Denoising for Online Conferencing Using CNN Architectures

Real-time FPGA implementation of the Semi-Global Matching stereo vision algorithm for a 4K/UHD video stream

An FPGA-Based Fully Pipelined Bilateral Grid for Real-Time Image Denoising

VIDOSAT: High-dimensional Sparsifying Transform Learning for Online Video Denoising

Block-Parallel Systolic-Array Architecture for 2-D NTT-based Fragile Watermark Embedding

Block-matching in FPGA

Related Research

Block-Matching Convolutional Neural Network for Image Denoising

New Computational Techniques for a Faster Variation of BM3D Image Denoising

Low Latency Video Denoising for Online Conferencing Using CNN Architectures

Real-time FPGA implementation of the Semi-Global Matching stereo vision algorithm for a 4K/UHD video stream

An FPGA-Based Fully Pipelined Bilateral Grid for Real-Time Image Denoising

VIDOSAT: High-dimensional Sparsifying Transform Learning for Online Video Denoising

Block-Parallel Systolic-Array Architecture for 2-D NTT-based Fragile Watermark Embedding