Automatic Translation of tock-CSP into Timed Automata

08/16/2020
by   Abdulrazaq Abba, et al.
0

The process algebra tock-CSP provides textual notations for modelling discrete-time behaviours, with the support of various tools for verification. Similarly, automatic verification of Timed Automata (TA) is supported by the real-time verification toolbox UPPAAL. TA and tock-CSP differ in both modelling and verification approaches. For instance, liveness requirements are difficult to specify with the constructs of tock-CSP, but they are easy to verify in UPPAAL. In this work, we translate tock-CSP into TA to take advantage of UPPAAL. We have developed a translation technique and tool; our work uses rules for translating tock-CSP into a network of small TA, which address the complexity of capturing the compositionality of tock-CSP . For validation, we use an experimental approach based on finite approximations to trace sets. We plan to use mathematical proof to establish the correctness of the rules that will cover an infinite set of traces.

READ FULL TEXT

page 1

page 2

page 3

page 4

research
04/27/2021

Temporal Reasoning Through Automatic Translation of tock-CSP into Timed Automata

In this work, we consider translating tock-CSP into Timed Automata for U...
research
10/05/2018

Towards a correct and efficient implementation of simulation and verification tools for probabilistic ntcc

We extended our simulation tool Ntccrt for probabilistic ntcc (pntcc) mo...
research
07/21/2020

Verification and Parameter Synthesis for Real-Time Programs using Refinement of Trace Abstraction

We address the safety verification and synthesis problems for real-time ...
research
11/07/2022

A Property Specification Pattern Catalog for Real-Time System Verification with UPPAAL

Context: The goal of specification pattern catalogs for real-time requir...
research
02/09/2022

An algebra of alignment for relational verification

Relational verification encompasses information flow security, regressio...
research
07/02/2020

Incremental methods for checking real-time consistency

Requirements engineering is a key phase in the development process. Ensu...
research
09/28/2022

Towards a Digital Highway Code using Formal Modelling and Verification of Timed Automata

One of the challenges in designing safe, reliable and trustworthy Autono...

Please sign up or login with your details

Forgot password? Click here to reset