Architecture-Aware, High Performance Transaction for Persistent Memory
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Byte-addressable non-volatile main memory (NVM) demands transactional mechanisms to access and manipulate data on NVM atomically. Those transaction mechanisms often employ a logging mechanism (undo logging or redo logging). However, the logging mechanisms bring large runtime overhead (8 evaluation), and 41 flushing. Such large overhead significantly diminishes the performance benefits offered by NVM. In this paper, we introduce a new method to remove the overhead of cache-line flushing for logging-based transactions. Different from the traditional method that works at the program level and leverages program semantics to reduce the logging overhead, we introduce architecture awareness. In particular, we do not flush certain cache blocks, as long as they are estimated to be eliminated out of the cache because of the caching mechanism (e.g., the cache replacement algorithm). Furthermore, we coalesce those cache blocks with low dirtiness to improve the efficiency of cache-line flushing. We implement an architecture-aware, high-performance transaction runtime system for persistent memory, Archapt. Our results show that comparing with the traditional undo logging, Archapt reduces cache flushing by 66 system throughput by 22 (A-F) with Redis, and TPC-C, LinkBench and YCSB with SQLite.
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