An ASIC Implementation and Evaluation of a Profiled Low-Energy Instruction Set Architecture Extension

by   Bobby Sleeba, et al.

This paper presents an extension to an existing instruction set architecture, which gains considerable reduction in power consumption. The reduction in power consumption is achieved through coding of the most commonly executed instructions in a short format done by the compiler based on a profile of previous executions. This leads to fewer accesses to the instruction cache and that more instructions can fit in the cache. As a secondary effect, this turned out to be very beneficial in terms of power. Another major advantage, which is the main concern of this paper is the reduction in the number of instruction fetch cycles which will also contribute significantly towards reduction in power consumption. The work involves implementing the new processor architecture in ASIC and estimation of power-consumption compared to the normal architecture.



There are no comments yet.


page 1

page 2

page 3

page 4


RVCoreP-32IM: An effective architecture to implement mul/div instructions for five stage RISC-V soft processors

RISC-V, an open instruction set architecture, is getting the attention o...

An Improving Method for Loop Unrolling

In this paper we review main ideas mentioned in several other papers whi...

A Lightweight ISA Extension for AES and SM4

We describe a lightweight RISC-V ISA extension for AES and SM4 block cip...

Extending the RISC-V ISA for exploring advanced reconfigurable SIMD instructions

This paper presents a novel, non-standard set of vector instruction type...

How the Mechanical Properties and Thickness of Glass Affect TPaD Performance

One well-known class of surface haptic devices that we have called TPaDs...

IChannels: Exploiting Current Management Mechanisms to Create Covert Channels in Modern Processors

To operate efficiently across a wide range of workloads with varying pow...

Stream Semantic Registers: A Lightweight RISC-V ISA Extension Achieving Full Compute Utilization in Single-Issue Cores

Single-issue processor cores are very energy efficient but suffer from t...
This week in AI

Get the week's most popular data science and artificial intelligence research sent straight to your inbox every Saturday.