Adding Explicit Load-Acquire and Store-Release Instructions to the RISC-V ISA
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Weak memory models allow for simplified hardware and increased performance in the memory hierarchy at the cost of increased software complexity. In weak memory models, explicit synchronization is needed to enforce ordering between different processors. Acquire and release semantics provide a powerful primitive for expressing only the ordering required for correctness. In this project, we explore adding load-acquire and store-release instructions to the RISC-V ISA. We add support to the herd formal memory model, the gem5 cycle-approximate simulator, and the LLVM/Clang toolchain. Because these instructions do not exist in the RISC-V standard, there is an inherent urgency to ratify explicit load-acquire/store-release instructions in order to prevent multiple ABI implementations and ecosystem fragmentation. We found that for workloads with a high degree of sharing and heavy contention, the impact of less memory ordering is muted, but our changes successfully encode the semantics we desire.
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