## References

- [1] R. Alur and D.L. Dill. A theory of timed automata. Theoretical Computer Science, 126(2):183–235, 1994.
- [2] R. Alur, T. Feder, and T.A. Henzinger. The benefits of relaxing punctuality. Journal of the ACM (JACM), 43(1):116–146, 1996.
- [3] R. Alur and P. Madhusudan. Decision problems for Timed Automata: A Survey. Formal Methods for the Design of Real-Time Systems, pages 115–116, 2004.
- [4] Rajeev Alur and Thomas A. Henzinger. Real-time logics: complexity and expressiveness. Information and Computation, 104:35–77, May 1993.
- [5] E. Asarin, O. Maler, and A. Pnueli. On discretization of delays in timed automata and digital circuits. CONCUR’98 Concurrency Theory, pages 603–610, 1998.
- [6] D. Beyer. Improvements in BDD-based reachability analysis of timed automata. FME 2001: Formal Methods for Increasing Software Productivity, pages 318–343, 2001.
- [7] D. Beyer, C. Lewerentz, and A. Noack. Rabbit: A tool for BDD-based verification of real-time systems. In Computer Aided Verification, pages 122–125. Springer, 2003.
- [8] D. Beyer and A. Noack. Can decision diagrams overcome state space explosion in real-time verification? Formal Techniques for Networked and Distributed Systems-FORTE 2003, pages 193–208, 2003.
- [9] S. Blom, T. Deiß, N. Ioustinova, A. Kontio, J. van de Pol, A. Rennoch, and N. Sidorova. Simulated time for host-based testing with TTCN-3. Software Testing, Verification and Reliability, 18(1):29–49, 2008.
- [10] D. Bošnacki. Digitization of timed automata. In Proceedings of FMICS, volume 99, pages 283–302, 1999.
- [11] M. Bozga, O. Maler, and S. Tripakis. Efficient verification of timed automata using dense and discrete time semantics. Correct Hardware Design and Verification Methods, pages 702–702, 1999.
- [12] G. Chakravorty and P.K. Pandya. Digitizing interval duration logic. In Computer Aided Verification, pages 167–179. Springer, 2003.
- [13] E. Clarke, F. Lerda, and M. Talupur. An abstraction technique for real-time verification. Next Generation Design and Verification Methodologies for Distributed Embedded Control Systems, pages 1–17, 2007.
- [14] R. Eshuis and R. Wieringa. Tool support for verifying UML activity diagrams. Software Engineering, IEEE Transactions on, 30(7):437–447, 2004.
- [15] Clemens Fischer and Heike Wehrheim. Model-checking CSP-OZ specifications with FDR. In Proceedings of the 1st International Conference on Integrated Formal Methods, pages 315–334, London, UK, 1999. Springer-Verlag.
- [16] C. Furia, M. Pradella, and M. Rossi. Automated verification of dense-time MTL specifications via discrete-time approximation. FM 2008: Formal Methods, pages 132–147, 2008.
- [17] C.A. Furia and M. Rossi. A theory of sampling for continuous-time metric temporal logic. ACM Transactions on Computational Logic (TOCL), 12(1):8, 2010.
- [18] Carlo Alberto Furia and Matteo Rossi. On the expressiveness of MTL variants over dense time. In Proceedings of the 5th international conference on Formal modeling and analysis of timed systems, FORMATS’07, pages 163–178, Berlin, Heidelberg, 2007. Springer-Verlag.
- [19] T. Henzinger, Z. Manna, and A. Pnueli. What good are digital clocks? Automata, Languages and Programming, pages 545–558, 1992.
- [20] K.G. Larsen, M. Mikucionis, and B. Nielsen. Online testing of real-time systems using UPPAAL. Formal Approaches to Software Testing, pages 79–94, 2005.
- [21] J. Ouaknine. Digitisation and full abstraction for dense-time model checking. Tools and Algorithms for the Construction and Analysis of Systems, pages 23–37, 2002.
- [22] J. Ouaknine and J. Worrell. Revisiting Digitization, Robustness, and Decidability for Timed Automata. In Proceedings of 18th Annual IEEE Symposium on Logic in Computer Science, pages 198–207. IEEE, 2003.
- [23] J. Ouaknine and J. Worrell. Timed CSP = closed timed -automata. Nordic Journal of Computing, 10:1–35, 2003.

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