A Complexity Reduction Method for Successive Cancellation List Decoding
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This paper introduces a hardware complexity reduction method for successive cancellation list (SCL) decoders. Specifically, we propose to use a sorting scheme so that L paths with smallest path metrics are also sorted according to their path indexes for path pruning. We prove that using such scheme enables one to use (L/2 + 1)-to-1 multiplexers instead of L-to-1 multiplexers for memory copying operations in a hardware implementation of SCL decoding. We verify by FPGA implementations that the proposed method achieves significant gain in hardware complexity of SCL decoding.
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