
An Analog Neural Network Computing Engine using CMOSCompatible ChargeTrapTransistor (CTT)
An analog neural network computing engine based on CMOScompatible charg...
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MFNet: ComputeInMemory SRAM for Multibit Precision Inference using Memoryimmersed Data Conversion and Multiplicationfree Operators
We propose a codesign approach for computeinmemory inference for deep...
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A Microprocessor implemented in 65nm CMOS with Configurable and Bitscalable Accelerator for Programmable Inmemory Computing
This paper presents a programmable inmemorycomputing processor, demons...
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A Memristive Neural Network Computing Engine using CMOSCompatible ChargeTrapTransistor (CTT)
A memristive neural network computing engine based on CMOScompatible ch...
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EnergyEfficient TimeDomain VectorbyMatrix Multiplier for Neurocomputing and Beyond
We propose an extremely energyefficient mixedsignal approach for perfo...
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Three dimensional waveguideinterconnects for scalable integration of photonic neural networks
Photonic waveguides are prime candidates for integrated and parallel pho...
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A complete, parallel and autonomous photonic neural network in a semiconductor multimode laser
Neural networks are one of the disruptive computing concepts of our time. However, they fundamentally differ from classical, algorithmic computing in a number of fundamental aspects. These differences result in equally fundamental, severe and relevant challenges for neural network computing using current computing substrates. Neural networks urge for parallelism across the entire processor and for a colocation of memory and arithmetic, i.e. beyond von Neumann architectures. Parallelism in particular made photonics a highly promising platform, yet until now scalable and integratable concepts are scarce. Here, we demonstrate for the first time how a fully parallel and fully implemented photonic neural network can be realized using spatially distributed modes of an efficient and fast semiconductor laser. Importantly, all neural network connections are realized in hardware, and our processor produces results without pre or postprocessing. 130+ nodes are implemented in a largearea vertical cavity surface emitting laser, input and output weights are realized via the complex transmission matrix of a multimode fiber and a digital micromirror array, respectively. We train the readout weights to perform 2bit header recognition, a 2bit XOR and 2bit digital analog conversion, and obtain < 0.9 10^3 and 2.9 10^2 error rates for digit recognition and XOR, respectively. Finally, the digital analog conversion can be realized with a standard deviation of only 5.4 10^2. Our system is scalable to much larger sizes and to bandwidths in excess of 20 GHz.
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