Log In Sign Up

A Comparison of High-Level Design Tools for SoC-FPGA on Disparity Map Calculation Example

by   Shaodong Qin, et al.

Modern SoC-FPGA that consists of FPGA with embedded ARM cores is being popularized as an embedded vision system platform. However, the design approach of SoC-FPGA applications still follows traditional hardware-software separate workflow, which becomes the barrier of rapid product design and iteration on SoC-FPGA. High-Level Synthesis (HLS) and OpenCL-based system-level design approaches provide programmers the possibility to design SoC-FGPA at system-level with an unified development environment for both hardware and software. To evaluate the feasibility of high-level design approach especially for embedded vision applications, Vivado HLS and Altera SDK for OpenCL, representative and most popular commercial tools in market, are selected as evaluation design tools, disparity map calculation as targeting application. In this paper, hardware accelerators of disparity map calculation are designed with both tools and implemented on Zedboard and SoCKit development board, respectively. Comparisons between design tools are made in aspects of supporting directives, accelerator design process, and generated hardware performance. The results show that both tools can generate efficient hardware for disparity map calculation application with much less developing time. Moreover, we can also state that, more directives (e.g., interface type, array reshape, resource type specification) are supported, but more hardware knowledge is required, in Vivado HLS. In contrast, Altera SDK for OpenCL is relatively easier for software programmers who is new to hardware, but with the price of more resources usage on FPGA for similar hardware accelerator generation.


page 1

page 2

page 3

page 4


On The Design of a Light-weight FPGA Programming Framework for Graph Applications

FPGA accelerators designed for graph processing are gaining popularity. ...

OpenCL-based FPGA accelerator for disparity map generation with stereoscopic event cameras

Although event-based cameras are already commercially available. Vision ...

Module-per-Object: a Human-Driven Methodology for C++-based High-Level Synthesis Design

High-Level Synthesis (HLS) brings FPGAs to audiences previously unfamili...

A Comparative Study between HLS and HDL on SoC for Image Processing Applications

The increasing complexity in today's systems and the limited market time...

Programming abstractions for preemptive scheduling in FPGAs using partial reconfiguration

FPGAs are an attractive type of accelerator for all-purpose HPC computin...