1.5 bit-per-stage 8-bit Pipelined CMOS A/D Converter for Neuromophic Vision Processor

01/31/2017 ∙ by Yilei F. Li, et al. ∙ 0

Neuromorphic vision processor is an electronic implementation of vision algorithm processor on semiconductor. To image the world, a low-power CMOS image sensor array is required in the vision processor. The image sensor array is typically formed through photo diodes and analog to digital converter (ADC). To achieve low power acquisition, a low-power mid-resolution ADC is necessary. In this paper, a 1.8V, 8-bit, 166MS/s pipelined ADC was proposed in a 0.18 um CMOS technology. The ADC used operational amplifier sharing architecture to reduce power consumption and achieved maximum DNL of 0.24 LSB, maximum INL of 0.35 LSB, at a power consumption of 38.9mW. When input frequency is 10.4MHz, it achieved an SNDR 45.9dB, SFDR 50dB, and an ENOB of 7.33 bit.



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