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hXDP: Efficient Software Packet Processing on FPGA NICs
FPGA accelerators on the NIC enable the offloading of expensive packet p...
10/27/2020 ∙ by Marco Spaziani Brunella, et al. ∙
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Micro SIDs: a solution for Efficient Representation of Segment IDs in SRv6 Networks
The Segment Routing (SR) architecture is based on loose source routing. ...
07/23/2020 ∙ by Angelo Tulumello, et al. ∙
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LOcAl DEcisions on Replicated States (LOADER) in programmable data planes: programming abstraction and experimental evaluation
Programmable data planes recently emerged as a prominent innovation in S...
01/21/2020 ∙ by German Sviridov, et al. ∙
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