research
∙
05/05/2021
CoSA: Scheduling by Constrained Optimization for Spatial Accelerators
Recent advances in Deep Neural Networks (DNNs) have led to active develo...
share
research
∙
04/26/2021
HAO: Hardware-aware neural Architecture Optimization for Efficient Inference
Automatic algorithm-hardware co-design for DNN has shown great success i...
research
∙
06/12/2020
CoDeNet: Algorithm-hardware Co-design for Deformable Convolution
Deploying deep learning models on embedded systems for computer vision t...
research
∙
05/27/2020
ProTuner: Tuning Programs with Monte Carlo Tree Search
We explore applying the Monte Carlo Tree Search (MCTS) algorithm in a no...
research
∙
03/02/2020
AutoPhase: Juggling HLS Phase Orderings in Random Forests with Deep Reinforcement Learning
The performance of the code a compiler generates depends on the order in...
research
∙
02/19/2020
Algorithm-hardware Co-design for Deformable Convolution
FPGAs provide a flexible and efficient platform to accelerate rapidly-ch...
research
∙
01/15/2019
AutoPhase: Compiler Phase-Ordering for High Level Synthesis with Deep Reinforcement Learning
The performance of the code generated by a compiler depends on the order...
research
∙
11/21/2018
Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAs
Using FPGAs to accelerate ConvNets has attracted significant attention i...
research
∙
04/28/2017
Proceedings of the 3rd International Workshop on Overlay Architectures for FPGAs (OLAF 2017)
The 3rd International Workshop on Overlay Architectures for FPGAs (OLAF ...
research
∙
06/21/2016
High Level Synthesis with a Dataflow Architectural Template
In this work, we present a new approach to high level synthesis (HLS), w...
research
∙
05/26/2016