D-RaNGe: Violating DRAM Timing Constraints for High-Throughput True Random Number Generation using Commodity DRAM Devices
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DRAM provides a promising substrate for generating random numbers due to three major reasons: 1) DRAM is composed of a large number of cells that are susceptible to many different failure modes that can be exploited for random number generation, 2) the high-bandwidth DRAM interface provides support for high-throughput random number generation, and 3) DRAM is prevalent in many commodity computing systems today, ranging from embedded devices to high-performance computing platforms. In this work, we propose a new DRAM-based true random number generator (TRNG) that exploits error patterns resulting from the deliberate violation of DRAM read access timing specifications. Specifically, by decreasing the DRAM row activation latency (tRCD) below manufacturer-recommended specifications, we induce read errors, or activation failures, that exhibit true random behavior. We then aggregate the resulting data from multiple cells to obtain a TRNG capable of continuous high-throughput operation. To demonstrate that our TRNG design is viable on commodity DRAM chips, we rigorously characterize the behavior of activation failures in 282 state-of-the-art LPDDR4 devices from across three major DRAM vendors and verify our observations using four additional DDR3 DRAM devices drawn from the same vendors. Our results show that many cells in each device produce random data that remains robust over both time and temperature variation. We use our observations to develop D-RaNGe, a methodology for extracting true random numbers from commodity DRAM devices with high throughput using access latency violation. We evaluate the quality of D-RaNGe using the NIST statistical test suite for randomness and find that D-RaNGe: 1) successfully passes each test, and 2) generates true random numbers with over two orders of magnitude higher throughput when compared with the previous highest-throughput DRAM-based TRNG.
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